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Synfora Joins Cadence Connections Program to Provide Tightly Integrated Algorithm-to-Tapeout Synthesis
Synfora's PICO Express Enables Architectural Exploration of ICs
and Accelerates Both RTL Creation and Time to Market
MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—June 1, 2004—
Synfora, Inc. announced that it has joined the Cadence Design
Systems, Inc. Connections(R) program and will be integrating its PICO
Express into the Cadence(R) synthesis, simulation, and verification
environments. By attracting best-in-class members, the Cadence
Connections program offers the industry's largest collection of
third-party solutions operating fully with the Cadence suite of design
tools. Synfora's integration with Cadence's platforms, enabled through
membership in Connections, will make available to mutual customers the
time and cost advantages of using PICO Express for integrated circuit
(IC) design.
"We are pleased to be a member of the Connections program," said
Simon Napper, Synfora's president and CEO. "Algorithm-to-tapeout
synthesis provides significant productivity benefits. By integrating
with Cadence tools, we can give customers a seamless
algorithm-to-tapeout flow that can help them ensure faster
time to market."
Synfora plans to integrate PICO Express with Cadence BuildGates(R)
synthesis, Cadence NC-Verilog(R) simulator, the Cadence Incisive(TM)
functional verification platform, and the Cadence Encounter(TM)
digital IC design platform.
About Synfora PICO Express
PICO Express, the first algorithm-to-tapeout synthesis tool,
enables design engineers to perform "what-if" analysis of chip
architectures, and then automatically creates efficient hardware from
algorithmic C descriptions. PICO Express leverages Synfora's
customizable Pipeline of Processor Array architecture to generate
efficient hardware. The architecture is highly flexible, allowing PICO
Express to automatically tailor the hardware to the precise algorithm.
This reduces from months to days the time to create
register-transfer-level (RTL) code. It also lowers verification cost
by using previously verified blocks and correct-by-construction
synthesis, and by automatically generating a test bench to test the
RTL. In addition, PICO Express lets designers find an optimal
implementation efficiently and explore the algorithm for better
alternatives.
About the Cadence Connections Program
The Cadence Connections program promotes open interoperability in
all areas of electronic design, including digital, custom IC,
analog/mixed-signal, and PCB design. By attracting best-in-class
members, Cadence offers the industry's largest collection of
third-party solutions operating fully with the Cadence suite of design
tools. The Connections program has over 120 member companies working
toward developing an optimized silicon design chain for customers.
Information about the Connections program may be found at
www.connectionsprogram.com.
About Synfora, Inc.
Founded in 2003, Synfora, Inc. is a venture-funded company that
delivers the first true "algorithm-to-tapeout" synthesis technology,
enabling IC designers to rapidly explore and implement C algorithms in
silicon. Synfora's algorithmic synthesis technology -- PICO (Program
In Chip Out) -- significantly reduces time to market and design risks
by exploring architecture alternatives and creating efficient RTL
code. Fore more information about Synfora and PICO technology, visit
www.synfora.com.
Synfora and the Synfora logo are trademarks of Synfora, Inc.
Cadence, BuildGates, and NC-Verilog are registered trademarks; and
Incisive and Encounter are trademarks of Cadence Design Systems, Inc.
All other names mentioned are trademarks, registered trademarks, or
service marks of their respective companies.
Contact:
Synfora, Inc.
Monica Nascimento, 650-314-0500 x110
monica@synfora.com
or
Armstrong Kendall, Inc.
Abbie Kendall, 503-672-4681
abbie@akipr.com
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